Multiple patterning is a technique used in photolithographic processes to allow for greater feature density. When fabricating integrated circuits, masks are used to selectively expose a photo-resist layer to a radiation (light) source. As the pattern density increases, it becomes more difficult to use masks with features in the low nanometer range because features that small are beyond the resolution of the light source. Thus, multiple masks may be used when two features in a particular pattern are too close to form in the same mask.
Additionally, integrated circuit fabrication involves the formation of several layers. Overlay control methods are used to ensure that each successive layer or mask is properly aligned to a previously deposited or formed layer. Nevertheless, there is typically a small overlay error for each alignment. For example, the overlay error may range between 5 and 10 nanometers. This overlay error can be even more problematic when using multiple patterning.